Simulation of intrinsic parameter fluctuations in nano-CMOS devices
As devices are scaled to gate lengths of sub 100 nm the effects of intrinsic parameter fluctuations will become increasingly important. This work presents a systematic simulation study of intrinsic parameter fluctuations, consisting of random dopant fluctations, line edge roughness and oxide thickness fluctuations, in a real 35 nm MOSFET developed by Toshiba. The simulations are calibrated against experimental data for the real device and it is found that discrete random dopants have the greatest impact on both the threshold voltage and leakage current fluctuations with a σVT of 33.2mV and a percentage increase in the average leakage current of 50%. Line edge roughness has the second greatest impact with a σVT of 19mV and percentage increase in the average leakage current of 45.5%. The smallest impact is caused by oxide thickness variations resulting in a σVT of 1.8mV and a 13% increase in the average leakage current. The combined effects of pairs of fluctuations is also studied, showing that these sources of intrinsic parameter fluctuations are statistically independent and a calculated σVT of 39mV is given for all of the sources combined. This value is on par with that reported in literature for the 90 nm technology node.