Direct digital synthesis by analogue interpolation
An improvement in efficiency of direct digital frequency synthesis (DDFS) systems is demanded for low power frequency synthesis in wireless communications. Concurrently a reduction in cost is important for disposable, low resolution frequency synthesis in biomedical instrumentation systems. To meet both these needs a new ROM-less architecture is presented here that uses less than half the circuit area of previous state of the art systems and improves the efficiency by operating at up to a tenth of the power consumption. The main contribution presented in this thesis is a novel, efficient method of interpolation for DDFS that uses the nonlinear response of the CMOS differential switch already present in the high speed current steering DAC. The nonlinear response provides a smooth transition between the conventional, quantised DAC output. This interpolation may be performed with the conventionally discarded phase bits leading to highly compact and efficient DDFS architectures for application in instrumentation and communications systems. DDFS systems typically consist of a large overflowing accumulator to generate the phase, a ROM lookup table to convert the phase to amplitude and a DAC to perform the digital to analogue conversion. Approximations are often used to reduce the size of the ROM, however the most efficient DDFS systems remove the ROM completely and calculate the phase to amplitude conversion directly or store the conversion in a non-linear DAC. State of the art, high speed CMOS DACs consisting of thermometer decoded arrays of current steering cells are often used to reduce non-ideal effects that cause unwanted transients leading to a degradation in spectral purity (SFDR). A novel ROM-less technique is introduced here that uses the non-linear response of a current cell consisting of an ideal current source and differential current switch to interpolate between the output levels of a non-linear DAC. Using this technique two architectures are developed. A compact architecture using only four or six current cells suitable for instrumentation applications and a thermometer decoded architecture using 64 current cells for communications applications that require better spectral purity. The compact architecture is 100% efficient as all the bias current is used to form the output. The only additional component is a small linear phase DAC. One compact system with a nonlinear DAC of four current cells achieved an SFDR of -40dBc up to output frequencies of 1MHz for dielectrophoresis consumed only 5μW/MHz and a second compact system with a six cell nonlinear DAC for electrical impedance spectroscopy, achieved an SFDR of -48dBc for output frequencies up to 1MHz and consumed only 8μW/MHz. As an extension to improve the SFDR a segmented system with 64 current cells was developed. The larger number of current cells required the use of a modified thermometer decoder that had the added benefit of improving the spectral purity by linearising the response of each cell. The total active area was 0.6mm2, less than half of state of the art ROM-less DDFS systems that include a DAC. Although measurement results of the 64 cell system were disappointing, simulations suggest that these problems may be solved in a future chip that should be able to achieve -70dBc SFDR at 100MHz. Despite the loss in performance from simulation to measurement, the measured 64 cell system still meets the spectral purity requirements of UMTS and Bluetooth, -60dBc SFDR.