Development of advanced technologies for the fabrication of III-V high electron mobility transistors
Over the past 5 years there has been an increase in the number of applications that require devices that operate in the millimetre range (30-300GHz). This demand has driven research into " devices that will operate at frequencies above 100GHz. This performance has been achieved using two main technologies, the Heterojunction Bipolar Transistor (HBT) and the High Electron Mobility Transistor (HEMT). At present it is a HEMT device that holds the record for the highest operating frequency of any transistor. It is this technology that this project concentrates on. In order to fabricate devices that operate at these frequencies two methods are commonly employed. The first is to vary the material of the device, in particular, increasing the indium content of the channel. The second method is to reduce the physical dimensions of the transistors, including reducing the gate length of the device therefore reducing transit time and gate capacitance. Reducing the separation of the source-drain ohmic contacts or employing a self-aligned ohmic strategy reduces the associated parasitic resistances. This project will concentrate on the scaling of the gate length in addition to the reduction of parasitic resistances with the use of self-aligned ohmic contacts. This work includes the realisation of the first self-aligned 120nm T -Gate. GaAs pHEMT fabricated at the University of Glasgow. These devices required the development of two key technologies, the non-annealed ohmic contact and the succinic acid based selective wet etch. The self-aligned devices showed good RF performance with a ft of 150 GHz and a fmax of 180 GHz which compares favourable with results o~ 120nm GaAs pHEMTs previously fabricated at Glasgow. The investigation of gate length scaling to device performance included the development of two lithographic process capable of producing HEMT with a gate length of 50nm and 30nm respectively in addition to a method ~f sample preparation that allows these devices to be analysed using TEM techniques. This work has lead to the realisation of SOnm T -gate metamorphic HEMTs using a PMMAIcopolymer resist stack, these devices displayed an excellent yield, with over 95% of devices working. The uniformity of the gate process was also high with a threshold voltage of - 0.44SV with a standard deviation of O.OOSV. The devices demonstrated an .it of 330GHz and a fmax of 260GHz making these devices some of the fastest transistors that have ever been fabricated on a GaAs substrate. The second lithography process was developed to realise T -gates with a gate length of less than SOnm. This processed used a two stage "bi-lithography" process to minimise the effect of forward s7attering through the resist. The gate footprint was transferred into a Si02 gate by a dry etch process. This lithography process was integrated into a full process flow for lattice matched InP HEMTs Using this process, HEMTs were fabricated with a T-gate of 2Snm. This is the smallest T -gate device that has been fabricated at the University of Glasgow and is comparable with the smallest HEMT devices in the world.