Low power digital self organising map
As the predicted application of the Self Organising Map, SOM, in portable devices makes power dissipation a critical design issue, recent hardware implementations of the SOM have focused on power. In more detail, the main principle shared among designers is to address power from the early stages of the design process. During the various phases of the process the power performance of differing design options should be estimated in order to choose the most power effective one. Clearly this level-by-level approach shortens times in comparison with a more old-fashioned approach which collects the feedback on the effect of a solution at the end of the process. The digital implementation of the SOM which is presented in this thesis achieves low power performance by means of reducing the number of clock cycles required to calculate the distance between one element of an input vector and the corresponding reference element in a neuron. This has resulted in the development of three designs of a neuron requiring two clock cycles, one clock cycle and half a clock cycle per element of the input vector. Detailed power figures for each model are given and the increase in silicon area, which allows for the reduction in clock cycles, is also discussed. Finally, the investigation moves to a higher level and the whole array of neurons is considered when the distance from an input vector is computed by all the neurons. Two methods which operate on the value of such a distance are illustrated as a way of reducing energy consumption. Both of them activate an automatic sleep mode within each neuron when the accumulated distance exceeds a given threshold. This is achieved by means of little additional hardware support. The energy performance achieved for three standard SOM benchmarks is discussed. In particular, the second method proves to guarantee an energy reduction of over 40%.