Optimisation studies on strain-engineered Germanium heterostructures
The physical gate lengths of state-of-the-art CMOS devices are 45 nm and are anticipated to reach just 20 nm by 2007. Due to the prohibitive capital expenditure required for next-generation CMOS technologies, leading device manufacturers are now exploring exotic device architectures and novel substrates in which significant device performance enhancements may by obtained using the existing device fabrication infrastructure. This thesis reports studies made on an initial evaluation of hole transport properties in strained Ge channels and comprises physical and electrical characterisation of these heterostructures as well as the analysis of SiGe layers using secondary ion mass spectrometry. The initial work of thesis describes the growth, characterisation and optimisation of a novel strained Ge substrate. The substrate technology was developed using a hybrid-epitaxy technique in which a SiGe strain-relaxed buffer layer, so called "virtual substrate", was grown using a ultra-high vacuum chemical-vapour deposition growth technique and the active strained Ge layer was grown using a solid-source molecular-beam epitaxy growth technology. An advanced chemical cleaning procedure has been developed which includes a modified Piranha etch. The novel cleaning procedure enables the successful integration of the two growth techniques. Significant hole carrier transport enhancements were observed for holes contained within the strained Ge channel. Optimisation of the hole mobility was achieved by the reduction of carrier scattering such as interface roughness scattering and point defect scattering. The optimisation methods employed included growth temperature iterations to reduce Ge channel roughening via elastic relaxation and, channel thickness iterations were also employed in order to minimize channel roughening and defect nucleation. Post-growth annealing procedures were used to combat defects arising from low temperature growth. The Ge heterostructures were grown on strain relaxed buffer layers, terminating with a Ge content of 60%. The optimised strained Ge channel thickness was found to be 20 nm and the growth temperature of the active layers was reduced to 350°C so as to minimise surface roughening. As grown point defects were eliminated at an optimised post-growth anneal temperature of 650°C for 30 minutes under dry N2• Hall mobilities reached 1910 cm2Ns at room temperature rising to 26,900 cm2Ns at 10K. A magneto-conductivity transfonnation measurement and maximum entropy mobility spectrum analysis revealed a room temperature drift mobility of 2700 cm2Ns at a carrier density of l.Ox1012 cm-2 . This result represents a 15-fo1d increase in hole mobility compared to conventional Si substrates at comparable effective fields. The second and important part of this thesis addresses charging effects observed when profiling undoped SiGe layers and the quantification of Ge fraction within SiGe layers using secondary ion mass spectrometry. Due to the highly resistive spreading resistance found for undoped SiGe layers when profiled using an O2+ incident beam, charging effects were found to mask the true layer profile. In order to overcome this problem a new approach is discussed for the first time. By illuminating the sample with a red laser light (wavelength 635mn) electron-hole pairs were created via photon absorption. The excess charge carriers were sufficient to overcome localised charging effects induced by the primary ion beam during SIMS analysis. In this manner, total charge suppression was achieved, thereby enabling a true determination of the SiGe sample profile to be obtained via SIMS. Finally, an analytical method enabling the accurate determination of Ge content of SiGe layers is discussed. The method employs a comparative ion yield methodology and enables both the spatial distribution and Ge concentration of SiGe layers to be accurately determined from a single SIMS measurement.