Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.382938
Title: Frame synchronisation methods for digital satellite system
Author: Shark, Lik
Awarding Body: Lancashire Polytechnic
Current Institution: University of Central Lancashire
Date of Award: 1988
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Abstract:
The research described in this thesis was carried out in four specific areas, namely, Satellite-Switched Time-Division Multiple-Access (SSTDMA) network synchronisation, frame synchronisers, remote sensing satellite data decommutating systems, and prototype frame synchroniser implementation. In the area of SSTDMA network synchronisation, this thesis reports several new synchronisation methods based on an original on-board synchronisation concept. These new methods are shown to have some significant advantages over existing methods. Also reported is a new algorithm to determine the exact satellite position for the open-loop three ranging stations method. In the area of frame synchronisers, adaptive control strategies and post-detection processing techniques are proposed for a new form of frame synchroniser. This new frame synchroniser is shown to provide reliable and optimum frame synchronisation operation in an unpredictable noisy environment. A high-speed version of the new frame synchroniser is also proposed, and it is shown that the adaptive control strategies may be implemented using a microprocessor-based system. In the area of remote sensing satellite data decommutating systems, this thesis reports a new system. Compared with existing systems, the proposed new system offers greater flexibility and expandability, with data decommutation and distribution carried out in real-time. A prototype adaptive frame synchroniser with post-detection processing was constructed, and tested under various simulated environmental conditions. The design and hardware implementation of the prototype frame synchroniser are described. The abilities of the prototype frame synchroniser, such as various mode transition strategies, automatic polarity correction, bit slippage tolerance up to ±2 bits and a bit error rate (BER) tolerance up to 0.208, were demonstrated via a range of tests, which are described in this thesis.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.382938  DOI: Not available
Keywords: Electronic & electrical engineering
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