An assessment of dual-rail encoded on-line test methodologies and their impact on ASIC/FPGA design
The testing of fabricated Integrated Circuits (IC's) is of great concern to production engineers and circuit designers alike. With the complexity of Very Large Scale Integrated (VLSI) circuits increasing every year, the problem of testing the fabricated designs is becoming acute. Several methods for reducing the burden of IC testing have been incorporated into the designs being tested thus giving rise to the phrase Design For Test (DFT). This thesis aims to understand how dual rail encoding of digital data can affect the different characteristics of electronic circuits. More specifically, it investigates a novel on-line test methodology called IFIS (If it Fails, It Stops), and its impact upon the design and implementation of electronic circuits intended for Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) technologies. The first two studies investigate the characteristics of the IFIS methodology to determine the most efficient and effective encoding scheme, protocol rules and feedback structures required for data processing. The third study investigates a series of possible improvements to the design of IFIS cells and determines the most efficient method of designing cells using the IFIS methodology. The final study investigates the feasibility of IFIS using a 'real life' commercial UART re-engineered using the IFIS methodology. The outcome of this work is an identification and characterisation of the factors which influence the performance and implementation cost of the IFIS methodology.