Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360803
Title: Architectural considerations for a control system processor
Author: Patel, Dipesh Ishwerbhai
Awarding Body: Loughborough University
Current Institution: Loughborough University
Date of Award: 1996
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Abstract:
Modern design methodologies for control systems create controllers with dynamics which are of a similar order to the physical system being controlled. When these are implemented digitally as Infinite Impulse Response (HR) filters the processing requirements are extensive, in particular when high sample rates are necessary to minimise the detrimental effects of sample delay. The aim of the research was to apply signal processing techniques to facilitate the implementation of control algorithms in digital form, with the principal objective of maximising the computational efficiency, either to achieve the highest possible sample rates using a given processor, or to minimise the processor complexity for a given requirement. One of the approaches is to design a fixed point processor whose architecture is optimised to meet the computational requirements of signal processing for control, thereby maximising what can be achieved with a single processor. Hence the aim of the research was to head towards a processor architecture optimised for Control System Processing. The design of this processor is based on a unified structural form and it will be shown that controllers, represented either in state space form or as transfer functions, can be implemented using this unified structure. The structure is based on the σ-operator, which has been shown to be robust to changes in coefficients and hence require shorter coefficient wordlength to achieve a comparable performance to traditional z-operator based structures. Additionally, the σ-operator structures are also shown to have lower wordlength requirements for the internal variables. Also presented is a possible architecture for a Control System Processor and a model for the processor is developed and constructed using VHDL. This is simulated on a test bench, also designed in VHDL. The results of implementing a phase advance controller on the processor are then compared with those obtained from a MATLAB simulation.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.360803  DOI: Not available
Keywords: Control processors ; Digital control implementation ; s-operator ; Structures for implementation ; s-operator state space structures ; ASIC's ; VHDL ; Architectures for control processors
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