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Title: Logic synthesis based on the Reed-Muller representation.
Author: Saul, Jonathan.
Awarding Body: University of Bristol
Current Institution: University of Bristol
Date of Award: 1991
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No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Circuits Electric circuits Electronic circuits Mathematics