Optical receiver design and optimisation for multi-gigahertz applications
This thesis is concerned with structures and design techniques appropriate for the realisation of integrated optical receivers operating at multi-gigahertz frequencies. The development and practical proving of novel signal designs tailored specifically to very high bit-rate optical communication systems is reported. Timing imperfections and signal dependent noise - a result of the optical amplification deployed in all high-performance systems - are two major impairments that must be accommodated if optimum system performance is to be achieved. Here, a signal design that accommodates these impairments is developed and compared to established designs. The new signal designs are shown to provide improved performance, in particular, they exhibit tolerance to uncertainty in the exact level of the impairment. Following the derivation of the signal designs a range of practical realisations are described. A receiver amplifier GaAs MMIC for 4.8 Gbit/s operation with embedded signal shaping is described followed by the design and test of integrated post-detection filters for 10 and 15 Gbit/s systems. The susceptibility of the embedded signal shaping receiver to variations in photodiode capacitance leads to the development and test of a low inputimpedance common-gate 5 Gbit/s GaAs MMIC receiver. To effect signal shaping at very high data-rates a modified distributed amplifier structure is proposed which better utilises the capabilities of the available foundry processes. Two distributed amplifier based optical receivers with embedded signal shaping are devised and simulation results for 10 Gbit/s show the efficacy of this design approach. The implications of noise matching are investigated and a 2 GHz SCM receiver is used as a vehicle to illustrate the methods developed. The long term goal of receiver design is to fully integrate bnth optical and electrical components onto a single chip. A preliminary investigation of the feasibility of this goal is carried out on an experimental InP-based process. Two receiver designs for 10 Gbit/s were prepared as a precursor to a detailed design of an OEIC with embedded signal shaping that incorporates the novel topologies developed during this work.