Relating formal models of concurrency for the modelling of asynchronous digital hardware
This Thesis investigates formal models of concurrency that are often used in the process of the design of asynchronous circuits, namely transition systems and Petri nets. The aim of the Thesis is to relate various classes of transition systems and nets, so that different models can be used at different design stages. We characterise three classes of transition systems: the sequential Semi-elementary Transition Systems, and two classes of step transition systems, where arcs are labelled by sets of concurrently executed events: TSENI and TSENIapost Transition Systems. All three classes can be employed to describe the behaviour of safe Petri nets used in circuit design. Semi-elementary Transition Systems are generated by Semi-elementary Net Systems, which are basically Elementary Net Systems with added self-loops. TSENI (TSENIapost ) Transition Systems are step transition systems generated by Elementary Net Systems with Inhibitor Arcs executed according to the a- priori (resp. a-posteriori) semantics, and called ENI-systems (resp. ENIapost -systems). The relationship between each class of transition systems and nets is established via the notion of a region in the process of solving the synthesis problem for the appropriate class of nets. The Thesis compares the three classes of transition systems and gives examples of their use in the specification of asynchronous circuits behaviour.