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Title: Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces.
Author: Cevik, Ulus.
ISNI:       0000 0001 3525 7162
Awarding Body: University of Sussex
Current Institution: University of Sussex
Date of Award: 1996
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No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Field programmable gate array