Toleranced multiple fault diagnosis of analogue circuits
The implementation of an automatic fault diagnosis approach for analogue circuits is facing a number of problem areas. They are typically: component and measurement tolerances, circuit size, limited observability constraints, multiple fault conditions, non-linear behaviour, speed and generic applicability. Since such fault finding techniques utilize circuit simulations sometime during the diagnostic process, the preferred form of classification amongst researchers is a taxonomy of Simulationbefore-Test (SbT) and Simulation-after-Test (SaT) methods. A survey of related work following these two strategies has been carried out, which concludes: The main advantage of the SaT strategy is their diagnostic power to cope with above problem areas, their main disadvantage is the often considerable computational on-line effort. The main advantage of the SbT strategy is on-line speed, but diagnostic power is often limited. What is needed is a workable solution to combine the advantages of the two strategies, whilst minimizing their disadvantages. The thesis is focused on this need. Subject of the research programme was therefore to look into the feasibility of a Simulation-before-Test approach for diagnosing toleranced analogue non-linear networks in the presence of multiple faults and from there to research the concepts, strategies and algorithms required to form a diagnostic approach.