Design techniques for enhancing the performance of frame buffer systems.
The 2D and 3D graphics support for PC's and workstations is becoming a very challenging
field. The need to continuously support real time image generation at higher frame rates
and resolutions implies that all levels of the graphics generation process must continuously
improve. New hardware algorithms need to be devised and the existing ones must be
optimised for better performance. These algorithms must exploit parallelism in every
possible way and new hardware architectures and memory configurations must accompany
them to support this kind ofparallelism.
This thesis focuses on new hardware techniques, of both architectural and algorithmic
nature, to accelerate the 2D and 3D graphics performance of computer systems. Some of
these new techniques are in the frame buffer access level, where the images are stored in the
video memory and then displayed on the screen. Some are in the rasterisation level where
the drawing of basic primitives such as lines, triangle and polygons takes place.
Novel rasterisation algorithms are invented and compared with traditional ones in terms of
hardware complexity and performance and their basic models have been implemented in
VHDL and in other software languages.
New frame buffer architectures are introduced and analysed that can improve the overall
performance of a graphics system significantly and are compatible with a number of
graphics systems in terms of their requirements.
During the development of this thesis special consideration was given to the hardware (e. g.
VHDL register-transfer level) implementation of the described architectures and algorithms.
Both software, hardware models and their test environments were implemented in a way to
maximise the accuracy of the results. The reason for that was to make sure that actual
hardware implementation would be possible and it would produce the same results without