Improved multidimensional digital filter algorithms using systolic structures
This work begins by explaining the issues in systolic array design. It continues by defining the criteria used in evaluating the quality of a design and its performance. An important feature of the approach taken in seeking to improve systolic systems has been the choice of target funtions. The rationale for these choices is explained and an underlying set of unifying key criteria are outlined which have been the basis of the design objectives in every case. In order to quantify improvements it is necessary to fully explore and document the current state of the art. This has been done by considering the best performing systems in each area of interest. One of the unifying principles for the research has been the derivation of all original and new designs from transfer functions. The detailed methods for mapping DSP algorithms systolic arrays are explored in word and bit level systems for multi-dimensional and median filters. The potential for improvement in the performance of systolic system implementation resides in two areas: improvement in the architectural structures of the arrays; and improvements in the speed and throughput of the processing elements. The programme of research has resulted in both these areas being addressed. In all, six new relaisatiions of two dimensional FIR and IIR filters are presented along with two new structures for the median filter. Additionally, a hybrid opto-electronic processing element has been devised which applies Fabry-Perrot resonators in a novel way. The basic adder structure is fully developed to demonstrate a high speed multiplier capability. An important issue for this research has been the verification of the correctness of designs and a confirmation of the efficacy of the theoretical calculated performances. The approach taken has been a two stage one in which a new circuit is first modelled at the behavioural level using the ELLA hardware description language. Having verified behavioural compliance the next stage is to model the system as a low level logic structure. This verifies the precise structures. The Mentor graphics architectural design tools were used for this purpose. In final impelementation as VLSI there would be a need to take into account chip layout related issues and these are discussed. The verification strategy of identifying and testing key structures is justified and evidence of successful stimulation is provided. The results are discussed in the context of comparing parameters of the new cirsuits with those of the previously best existing designs. The parameters tabulated are: data throughput rate; circuit latency; and circuit size (area). It is concluded that improvements are evident in the new designs and that they are highly regular structures with simple timing and control thus making them attractive for VLSI implementation. In summary, the new and original structures provide a better balance between cost and complexity. The new processing element system is theoretically capabale of operation in region of 4 nanoseconds per addition and new algorithm for median filtering promises a sharp improvement in speed.