Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503
Title: Optimising fault modelling and test development for VLSI analogue circuits
Author: Besnard, Stéphane Claude Louis.
Awarding Body: University of Huddersfield
Current Institution: University of Huddersfield
Date of Award: 2001
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Abstract:
No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.288503  DOI: Not available
Keywords: Electronic testing Electric engineering Computer science Electric measurements Electronic measurements
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