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Title: Methods for the atomistic simulation of ultrasmall semiconductor devices
Author: Arokianathan, Clinton Rudra
ISNI:       0000 0001 3429 6813
Awarding Body: University of Glasgow
Current Institution: University of Glasgow
Date of Award: 1998
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As the feature sizes in VLSI technology shrink to less than 100 nm the effects due to the quantisation of electronic charge begin to emerge. There are a small number of carriers and impurities and the statistical variation in their number have significant effects on the threshold characteristics of the devices that hamper their large scale integration into future ULSI.The complex potential landscape arising from the Coulomb force, with its sharp localised peaks and troughs, faces problems due to band limiting in meshes and places heavy burdens on the integration techniques. A computationally efficient solution to the problem of band-limiting is presented and is shown to provide an accurate description of the electrostatics. This work also introduces a highly efficient and numerically stable multigrid solver, for Poisson's equation, that can cope with the complex potential distributions on large meshes. The study of ionised impurity scattering is used to validate these molecular dynamics simulations. Results have shown that the Brownian method - despite precluding the use of adaptive integration schemes - gives a good approximation to the standard results and has the advantage of smoothing away errors that can build up during the integration of motion and drives the system towards thermal equilibrium. The greatest hurdle to be cleared before these three-dimensional simulations can be practicable is the sheer computational effort that is required. The implementation of the problem on parallel architectures has been explored and discussed. The methods developed in this work are demonstrated through the simulation of an 80 nm dual-gate MESFET. The results were verified by comparing them with those from a commercial drift-diffusion simulator. The threshold behaviour of devices has been investigated through the study of the formation of conduction channels in blocks. The percolation threshold gives the point when conductive paths form across the gate barrier. The results from the FET simulation were found to be in agreement with the earlier studies on the blocks.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: T Technology (General) Electric apparatus and appliances Electronic apparatus and appliances