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Title: High level synthesis for an area efficient datapath architecture
Author: Duncan, Andrew A.
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 1994
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The advances in integrated circuit fabrication technology, coupled with the emergence of independent silicon foundries, has made it commercially viable to fabricate low volume Application Specific Integrated Circuits (ASICs). However, given the complexity of such systems it is becoming uneconomical to design them using conventional computer aided design (CAD) techniques. One approach to solving the so called "design crisis" has been to develop design tools which can synthesise an entire silicon architecture from an algorithmic description of its functionality. Such systems are referred to as high level synthesis systems. Interconnect is a major cost in VLSI devices and its effects are difficult to estimate in high level synthesis. As such, many existing high level synthesis systems use quite weak interconnect estimation heuristics which lead to inefficient layout when the synthesised structure is mapped into the physical domain. The presented approach defines a partitioned target architecture and bit-sliced layout style which may virtually eliminate the need for global wiring and hence obviate the problem of interconnect estimation. The structural cost of the synthesised architecture is therefore more closely associated with the real physical cost when realised on chip. This target architecture is used as the basis for the CASS high level synthesis system which performs algorithmic behavioural synthesis for digital signal processing (DSP) applications. A detailed discussion of the algorithms in the CASS tools is given and presented area estimates show that significant area savings are attainable by using the defined architecture and layout style. The development of CASS inspired a successor system which performs high level synthesis in one global optimisation. COBRA performs synthesis by optimising a mapping of variable lifetimes in a three dimensional "datapath space" using the method of simulated annealing.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Integrated circuits