Integrated synthesis and timing analysis of synchronous digital systems
In recent years, there has been much discussion about the merits of the top-down design methodology. Studies show that a more successful design paradigm and, indeed, the one that human designers of circuits tend to use is one that combines bottom-up and top-down design. In this thesis we describe the development of a system that is able to combine the process of top-down refinement of a high-level design specification with the bottom-up process of speed assessment. The system is able to do so by virtue of the fact that its refinement algorithms always partition the circuit in a well-defined manner. We can therefore pre-characterize the speed of all such partition possibilities and use this information to guide the choice of partition. We then focus upon the problem of the accurate and efficient estimation of speed in VLSI circuits. Speed estimation has traditionally been performed by simulators and static timing analysers. Circuit simulation is both expensive and may exercise impossible paths, due to the fact that impossible input data was fed to the circuit or signals were diverted in the wrong direction through the circuit components. The path which a simulator tells us is the critical (slowest) path, may never be exercised during the circuit's normal use. Analysing the propagation of impossible data may therefore expose false critical paths and lead to pessimistic speed estimates. Static timing analysis is less expensive but assumes that every component in the circuit contributes its slowest possible delay. Pessimistic speed estimates result and, since the slowest rather than the actual delay contributions of some of the components are used, false critical paths may be discovered.