A design technique for mixed ECL and CMOS circuitry
In this thesis, the principles of mixing ECL and CMOS technologies have been investigated with the intention of increasing the operating speed of synchronous systems. To achieve this, the design will be primarily CMOS based with the critical path implemented in ECL to reduce the delay and hence improve the execution time. Logic conversion circuitry between the two technologies has been designed, with the CMOS-ECL conversion circuit being a simple enhancement of the basic ECL current switch and ECL-CMOS translation being achieved with 0.5ns using a "double inverter circuit". To reduce the power dissipation of the ECL circuitry, a power control circuit has been incorporated which enables the ECL circuitry when the critical path is required and disables it, to save power, when the instructions to be evaluated are non critical. To further reduce the power consumption of the ECL circuitry and decrease the execution time, a BiCMOS active pull down circuit has been added. The active pull down circuit replaces the resistor in the traditional emitter follower configuration, reducing the power loss and matching the gate fall time to the rise time. A mixed ECL and CMOS technology ripple adder, utilising all of these features, has been designed and simulated using HSPIC. The inputs to be added are from CMOS registers and the output sum is returned to CMOS registers but within the circuit, the carry ripple is implemented in ECL. The performance is comparable with an ECL adder whilst using less than a third of the power and with larger, more complex systems, the mixed technology concept is estimated to actually be faster than ECL.